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128kx36, sync lw, lvttl, rev 4.6 1 / 22 august 12, 1998 CXK77B3641GB sony 45/5/6 4mb late write lvttl high speed synchronous sram (128k x 36 organization) description features r-r mode r-l, r-ft modes ? fast cycle/access time t khkh / t khqv t khkh / t khqv cxk77b3641 -45 4.5ns / 2.4ns 5.5ns / 5.5ns -5(*) 5.0ns / 2.5ns 5.7ns / 5.7ns -6 6.0ns / 3.0ns 6.0ns / 6.0ns note (*): contact sony memory marketing for availability of -5 speed bin. ? 3 synchronous modes of operation, selectable by mode pins: register-register; register-latch; register-flow thru; ? single +3.3v power supply: 3.3v 5% ? dedicated output supply voltage: v ddq (2.5v to 3.3v typical) ? inputs and outputs are lvttl/lvcmos compatible. ? differential clock input (k/k ). clock levels are compatible to pecl, lvttl and lvcmos. ? all inputs (except asynchronous g and zz) and outputs are registered on a single clock edge. ? byte write capability. ? late write scheme to eliminate one dead cycle from read-to-write transitions. ? self-timed write cycles. ? sleep (power down) mode. ? jtag boundary scan (subset of ieee standard 1149.1). ? 119 pin (7x17) plastic ball grid array (pbga) package. the cxk77b3641 is a high speed bicmos synchronous static ram with common i/o pins, organized as 131,072-words by 36-bits. this synchronous sram integrates input registers, high speed ram, output registers/latches, and a one-deep write buffer onto a single monolithic ic. three different read protocols - register-register (r-r), register-latch (r-l), and registe r- flow thru (r-ft), and an enhanced write protocol - late (delayed) write (lw), are supported, providing a flexible, high-per- formance user interface. all input signals except g (output enable) and zz (sleep mode) are registered on the positive edge of k clock. read cycles can be controlled in one of three ways - with registered outputs in register-register mode, with latched outputs in register-latch mode, or with flow-through outputs in register-flow thru mode. the read protocol is user-selectable through external mode pins m1 and m2. write cycles follow a late write protocol, where data is provided to the sram one clock cycle after the address and control signals, eliminating one dead cycle from read-to-write transitions. in this scheme, when a write cycle is initiated, the addres s and data stored in the srams write buffer during the previous write cycle are directed to the srams memory core, while, simultaneously, the address and data from the current write cycle are stored in the srams write buffer. in both register-latch and register-flow thru modes, when sw (global write enable) is driven active, the subsequent positive edge of k clock tri- states the srams output drivers immediately, allowing consecutive read-write-read operations. the write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. sleep (power down) mode control is provided through the asynchronous zz input. 220 mhz operation is obtained from a single 3.3v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
128kx36, sync lw, lvttl, rev 4.6 2 / 22 august 12, 1998 sony ? CXK77B3641GB pin configuration (top view) pin description 1234567 a v ddq sa6 sa7 nc sa3 sa2 v ddq b nc nc sa8 nc sa4 nc nc c nc sa12 sa5 vdd sa0 sa13 nc d dq7c dq8c v ss nc v ss dq8b dq7b e dq5c dq6c v ss ss v ss dq6b dq5b f v ddq dq4c v ss g v ss dq4b v ddq g dq2c dq3c sbw cc sbw b dq3b dq2b h dq0c dq1c v ss cv ss dq1b dq0b j v ddq v dd nc v dd nc v dd v ddq k dq0d dq1d v ss kv ss dq1a dq0a l dq2d dq3d sbw dk sbw a dq3a dq2a m v ddq dq4d v ss sw v ss dq4a v ddq n dq5d dq6d v ss sa14 v ss dq6a dq5a p dq7d dq8d v ss sa11 v ss dq8a dq7a r nc sa10 m1 v dd m2 sa15 nc t nc nc sa9 sa16 sa1 nc zz u v ddq tms tdi tck tdo nc v ddq symbol description symbol description symbol description sa address input (0-16) g async. output enable v ddq output power supply dq data i/o (0-8), bytes a-d zz async. sleep mode v ss ground k,k differential input clocks tck jtag clock (lvttl) m1,m2 mode select c,c differential output control clocks (for future use) tms jtag mode select (lvttl) nc no connect sw write enable, global tdi jtag data in (lvttl) sbw x write enable, bytes a-d tdo jtag data out (lvttl) ss synchronous select v dd +3.3v power supply
128kx36, sync lw, lvttl, rev 4.6 3 / 22 august 12, 1998 sony ? CXK77B3641GB add. write pulse 128k x 36 dout din 2:1 mux output latch reg. 2:1 mux input reg. write store reg. read comp. reg. reg. reg. self time write logic output clock mode control sa 0-16 ss sw sbw a-d 4 17 k/k m1 m2 g dq ^ ^ ^ ^ block diagram clock input 2 kint kint kint kint kint
128kx36, sync lw, lvttl, rev 4.6 4 / 22 august 12, 1998 sony ? CXK77B3641GB ? tr uth tables register - register mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq 0-35 (t n ) dq 0-35 (t n+1 ) v dd current h x x x x sleep mode. power down hi - z hi - z i sb l h x x x deselect x hi - z i dd l l h x h read hi - z hi - z i dd l l h x l read x q(t n )i dd l l l l x write all bytes (bits 0-35) x d(t n )i dd l l l x x write bytes with sbw x=l x d(t n )i dd l l l h x abort write x hi - z i dd register - latch and register - flow thru mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq 0-35 (t n ) dq 0-35 (t n+1 ) v dd current h x x x x sleep mode. power down hi - z hi - z i sb l h x x x deselect hi - z x i dd l l h x h read hi - z hi - z i dd l l h x l read q(t n )x i dd l l l l x write all bytes (bits 0-35) hi - z d(t n )i dd l l l x x write bytes with sbw x=l hi - z d(t n )i dd l l l h x abort write hi - z x i dd
128kx36, sync lw, lvttl, rev 4.6 5 / 22 august 12, 1998 sony ? CXK77B3641GB ? mode select this device supports three different jedec standard read protocols via mode pins m1 and m2. the mode pins must be set during power-up and cannot change during sram operation. mode select truth table . ? power-up sequence power supplies must power up in the following sequence: v ss , v dd , v ddq , and inputs. v ddq must never exceed v dd . ? absolute maximum ratings (1) (1) stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. m1 m2 register-register l h register-flow thru l l register-latch h l item symbol rating unit supply voltage v dd -0.5 to +4.6 v output supply voltage v ddq -0.5 to +4.6 v input voltage v in -0.5 to v dd +0.5 (4.6v max.) v output voltage v out -0.5 to v ddq +0.5 (4.6v max.) v operating temperature t a 0 to 70 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c
128kx36, sync lw, lvttl, rev 4.6 6 / 22 august 12, 1998 sony ? CXK77B3641GB ? dc recommended operating conditions ( v ss = 0v , t a = 0 to 70 o c) (1) for v ddq = 2.5v or v ddq = 3.3v application. (2) v ih (max) ac = v dd +1.5 v for pulse width less than 2.0 ns (3) v ih (max) ac = v ddq +1.5 v for pulse width less than 2.0 ns (4) v il (min) ac = -1.5 v for pulse width less than 2.0 ns. (5) this device supports three different input clocking schemes: a. lvttl differential - in this scheme, both clock inputs (k and k ) are driven differentially to the same voltage levels as the other inputs, i.e. from v ss to v ddq nominally. v kin , v dif , and v cm must all be considered when using this scheme. b. lvttl single ended - in this scheme, one of the two clock inputs (either k or k ) is driven to the same voltage levels as the other inputs, i.e. from v ss to v ddq nominally, while the other clock input (ei- ther k or k) is tied to an external reference voltage (v x ). v kin , v dif , and v x must all be considered when using this scheme. c. pecl differential - in this scheme, both clock inputs (k and k ) are driven differentially according to pecl guidelines. both v ih-pecl and v il-pecl must be considered when using this scheme. ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. item symbol min typ max unit supply voltage v dd 3.13 3.3 3.47 v output supply voltage (1) v ddq 2.37 2.5, 3.3 3.47 v address & control input high voltage (2) v ihca 1.65 --- v dd + 0.3 v input low voltage (4) v ilca -0.3 --- 1.15 v data input high voltage (3) v ihd 1.65 --- v ddq + 0.3 v input low voltage (4) v ild -0.3 --- 1.15 v clock (5) lvttl input signal voltage v kin -0.3 --- v dd + 0.3 v input dif ferential voltage v dif 0.5 --- v dd + 0.6 v input common mode voltage v cm 1.15 1.4 1.75 v input cross point voltage v x 1.15 1.4 1.75 v pecl input high voltage v ih-pecl 2.135 --- 2.420 v input low voltage v il-pecl 1.480 --- 1.825 v item symbol test conditions min max unit input capacitance c in v in = 0v --- 6 pf clock input capacitance c clk v in = 0v --- 6 pf output capacitance c out v out = 0v --- 7 pf
128kx36, sync lw, lvttl, rev 4.6 7 / 22 august 12, 1998 sony ? CXK77B3641GB ? dc electrical characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 70 o c) 1. typical i dd values measured at v dd = 3.3v and t a = 25 o c, with a 75% read / 25% write operation distribution. item symbol test conditions min typ max unit input leakage current i li v in = v ss to v dd -1 --- 1 ua output leakage current i lo v out = v ss to v dd g = v ih -10 --- 10 ua power supply operating current i dd 1 cycle = 6.0ns duty = 100% i out = 0 ma --- 665 --- ma power supply operating current i dd 1 cycle = 5.5ns duty = 100% i out = 0 ma --- 695 --- ma power supply operating current i dd 1 cycle = 4.5ns duty = 100% i out = 0 ma --- 755 --- ma power supply standby current i sb zz 3 v ih --- 60 --- ma output high voltage v ddq = 3.3v v oh i oh = -6.0 ma 2.4 --- --- v output low voltage v ddq = 3.3v v ol i ol = 6.0 ma --- --- 0.4 v output high voltage for v ddq = 2.5v v oh i oh = -6.0 ma 2.0 --- --- v output low voltage for v ddq = 2.5v v ol i ol = 6.0 ma --- --- 0.4 v
128kx36, sync lw, lvttl, rev 4.6 8 / 22 august 12, 1998 sony ? CXK77B3641GB ? ac electrical characteristics (register-register mode ) 1. all parameters are specified over the range t a = 0 to 70 o c. 2. these parameters are sampled and are not 100% tested. item symbol -45 -5 -6 unit min max min max min max cycle time t khkh 4.5 --- 5.0 --- 6.0 --- ns clock high pulse width t khkl 1.5 --- 1.5 --- 2.0 --- ns clock low pulse width t klkh 1.5 --- 1.5 --- 2.0 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 2.4 --- 2.5 --- 3.0 ns clock high to output hold t khqx *2 0.7 --- 0.7 --- 0.7 --- ns clock high to output low-z t khqx1 *2 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z (ss deselect cycle) t khqz *2 --- 2.0 --- 2.0 --- 2.0 ns output enable low to output valid t glqv --- 2.3 --- 2.5 --- 3.0 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.3 --- 2.5 --- 3.0 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 ns
128kx36, sync lw, lvttl, rev 4.6 9 / 22 august 12, 1998 sony ? CXK77B3641GB ? ac electrical characteristics (register-latch & register-flow thru modes) 1. all parameters are specified over the range t a = 0 to 70 o c. 2. these parameters are sampled and are not 100% tested. item symbol -45 -5 -6 unit min max min max min max cycle time t khkh 5.5 --- 5.7 --- 6.0 --- ns clock high pulse width t khkl 1.5 --- 1.5 --- 2.0 --- ns clock low pulse width t klkh 1.5 --- 1.5 --- 2.0 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 5.5 --- 5.7 --- 6.0 ns clock high to output hold (flow thru mode only) t khqx *2 2.0 --- 2.0 --- 2.0 --- ns clock high to output low-z (flow thru mode only) t khqx1 *2 2.0 --- 2.0 --- 3.0 --- ns clock low to output valid (latch mode only) t klqv --- 2.3 --- 2.5 --- 2.5 ns clock low to output hold (latch mode only) t klqx *2 0.7 --- 0.7 --- 0.7 --- ns clock low to output low-z (latch mode only) t klqx1 *2 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z (ss deselect cycle) t khqz *2 --- 2.0 --- 2.0 --- 2.0 ns clock high to output high-z (sw write cycle) t khqz1 *2 --- 2.0 --- 2.0 --- 2.0 ns output enable low to output valid t glqv --- 2.3 --- 2.5 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.3 --- 2.5 --- 2.5 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 ns
128kx36, sync lw, lvttl, rev 4.6 10 / 22 august 12, 1998 sony ? CXK77B3641GB ? ac test conditions (v ddq = 2.5v) (v dd = 3.3v 5%, v ddq = 2.5v -5%/+10%, t a = 0 to 70 c) item conditions notes address / control / data input high level v ihca , v ihd = 2.0v @ set up time 31 ns address / control / data input low level v ilca , v ild = 0.8v @ set up time 31 ns input rise & fall time 1.0v/ns other than clock input reference level 1.4v other than clock clock lvttl input high voltage 2.2v v dif 3 0.8v lvttl input low voltage 0.6v v dif 3 0.8v lvttl input common mode voltage 1.4v pecl input high voltage v ih-pecl = 2.3v pecl input low voltage v il-pecl = 1.6v clock input rise & fall time 1.0v/ns clock input reference level k/k cross output reference level 1.25v output load conditions fig.1 dq 1.25 v fig. 1: ac test output load (v ddq = 2.5v) 50 w 50 w 5 pf 16.7 w 1.25 v 50 w 50 w 5 pf 16.7 w 16.7 w
128kx36, sync lw, lvttl, rev 4.6 11 / 22 august 12, 1998 sony ? CXK77B3641GB ? ac test conditions (v ddq = 3.3v) (v dd = v ddq = 3.3v 5%, t a = 0 to 70 c ) item conditions notes address / control / data input high level v ihca , v ihd = 2.4v @ set up time 31 ns address / control / data input low level v ilca , v ild = 0.4v @ set up time 31 ns input rise & fall time 1.0v/ns other than clock input reference level 1.4v other than clock clock lvttl input high voltage 2.4v v dif 3 1.0v lvttl input low voltage 0.4v v dif 3 1.0v lvttl input common mode voltage 1.4v pecl input high voltage v ih-pecl = 2.3v pecl input low voltage v il-pecl = 1.6v clock input rise & fall time 1.0v/ns clock input reference level k/k cross output reference level 1.4v output load conditions fig.2 dq 1.4 v fig. 2: ac test output load (v ddq = 3.3v) 50 w 50 w 5 pf 16.7 w 1.4 v 50 w 50 w 5 pf 16.7 w 16.7 w
128kx36, sync lw, lvttl, rev 4.6 12 / 22 august 12, 1998 sony ? CXK77B3641GB t svkh t khsx t khqv t khqx1 t ghqz t glqv t glqx t khqv qn t khqz sw k k timing waveform of read cycle qn-2 nn+1 qn-1 n+2 sa0-sa16 g dq0-dq35 t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss timing waveform of write cycle g ss sw /sbw x k n n+1 n+2 k sa0-sa16 dn dn+1 dq0-dq35 t khdx t dvkh dn-1 register - register mode
128kx36, sync lw, lvttl, rev 4.6 13 / 22 august 12, 1998 sony ? CXK77B3641GB sa0-sa16 ss g = vil dq0-dq35 timing waveform of read-write-read cycle i ( ss controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x qn-1 qn dn+2 qn+3 read n deselect (hi z) write n+2 read n+3 sa0-sa16 ss = vil g dq0-dq35 timing waveform of read-write-read cycle ii ( g controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x qn-1 qn dn+2 qn+3 read n hi z; read n+3 write n+2 register - register mode
128kx36, sync lw, lvttl, rev 4.6 14 / 22 august 12, 1998 sony ? CXK77B3641GB t svkh t khsx t khqv t ghqz t glqv t glqx t khqv qn+1 t khqz sw k k timing waveform of read cycle qn-1 nn+1 qn n+2 sa0-sa16 g dq0-dq35 t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss t klqv t klqx1 t klqv t svkh t khsx timing waveform of write cycle g ss sw /sbw x k n n+1 n+2 k sa0-sa16 dn dn+1 dq0-dq35 t khkh t khdx t dvhk dn-1 register - latch mode
128kx36, sync lw, lvttl, rev 4.6 15 / 22 august 12, 1998 sony ? CXK77B3641GB sa0-sa16 ss g = vil dq0-dq35 k k n n+2 n+3 n+4 n+5 sw /sbw x qn dn+1 qn+4 read n deselect (hi z) read n+2 read n+4 n+1 qn+2 write n+1 t khqv t khqz1 t dvkh t khwx t av k h t khax t klqx1 t wvkh t svkh t khdx t khsx t klqv t klqv t klqv t khkh t khkh t khkh t khkh t khqv timing waveform of read-write-read cycle t khqz register - latch mode
128kx36, sync lw, lvttl, rev 4.6 16 / 22 august 12, 1998 sony ? CXK77B3641GB t svkh t khsx t khqv t khqx1 t ghqz t glqv t glqx t khqv qn+1 t khqz sw k k timing waveform of read cycle qn-1 nn+1 qn n+2 sa0-sa16 g dq0-dq35 t wvkh t av k h t khxw t khax t khkh t khkl t klkh ss t svkh t khsx timing waveform of write cycle g ss sw /sbw x k n n+1 n+2 k sa0-sa16 dn dn+1 dq0-dq35 t khdx t dvkh dn-1 register - flow thru mode
128kx36, sync lw, lvttl, rev 4.6 17 / 22 august 12, 1998 sony ? CXK77B3641GB sa0-sa16 ss g = vil dq0-dq35 k k n n+2 n+3 n+4 n+5 sw /sbw x qn dn+1 qn+4 read n deselect (hi z) read n+2 read n+4 n+1 qn+2 write n+1 t khqv t khqz1 t dvkh t khwx t av k h t khax t wvkh t svkh t khdx t khsx t khqv t khqx1 t khqv timing waveform of read-write-read cycle t khqz register - flow thru mode
128kx36, sync lw, lvttl, rev 4.6 18 / 22 august 12, 1998 sony ? CXK77B3641GB test mode description functional description the cxk77b3641 provides a jtag boundary scan interface using a limited set of ieee std. 1149.1 functions. the test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), srams, other components and the printed circuit board. in conformance with a subset of ieee std. 1149.1, the cxk77b3641 contains a tap controller, instruc- tion register, boundary scan register and bypass register. jtag inputs/outputs are lvttl compatible only. test access port (tap) 4 pins as defined in the pin description table are used to perform jtag functions. the tdi input pin is used to scan test data serially into one of three registers (instruction register, boundary scan register and bypass register). tdo is the output pin used to scan test data serially out. the tdi pin sends the data into lsb of the selected register and the msb of the selected register feeds the data to tdo. the tms input pin controls the state transition of 16 state tap controller as specified in ieee std. 1149.1. inputs on tdi and tms are registered on the rising edge of tck clock. the output data on tdo is presented on the falling edge of tck. tdo driver is in active state only when tap controller is in shift-ir state or in shift-dr state. tck, tms, tdi must be tied low when jtag is not used. tap controller 16 state controller is implemented as specified in ieee std. 1149.1. the controller enters reset state in one of two ways: 1. power up. 2. apply a logic 1 on tms input pin on 5 consecutive tck rising edges. instruction register (3 bits) the jtag instruction register consists of a shift register stage and parallel output latch. the register is 3 bits wide and is encoded as follow: octal msb..........lsb instruction 0 0 0 0 bypass 1 0 0 1 idcode. read device id 2 0 1 0 sample-z. sample inputs and tri-state dqs 3 0 1 1 bypass 4 1 0 0 sample. sample inputs. 5 1 0 1 private. manufacturer use only. 6 1 1 0 bypass 7 1 1 1 bypass
128kx36, sync lw, lvttl, rev 4.6 19 / 22 august 12, 1998 sony ? CXK77B3641GB bypass register (1 bit) the bypass register is one bit wide and is connected electrically between tdi and tdo and provides the minimum length serial path between tdi and tdo. id registers (32 bits) the id register is 32 bits wide and is encoded as follows: boundary scan register (70 bits) the boundary scan registers are 70 bits wide and are listed as follows: k/k , c/c inputs are sampled through one differential stage and internally inverted to generate internal k/k , c/c signals for scan registers. place holder are required for some nc pins to maintain 70 bits scan register for different types of the same family sram and for density upgrades. all place holder reg- isters are connected to v ss internally regardless of pin connection externally. tnc register is true no connect i.e. not connected internally. tnc register information should be ignored during bscan test- ing. id[0} 1 sony id id[11:1] 0000 1110 001 part number id[27:12] 0000 0000 0001 1001 revision number id[31:28] xxxx dq 36 sa 17 sw , sbw x5 ss , g 2 k, k , c, c 4 zz 1 m1, m2 2 place holder 2 tnc 1
128kx36, sync lw, lvttl, rev 4.6 20 / 22 august 12, 1998 sony ? CXK77B3641GB scan order (order by exit sequence) (*) tnc means that the voltage polarity of this bit should be ignored during boundary scan testing. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 3b - 3a 3c 2c 2a 2d 1d 2e 1e 2f 2g 1g 2h 1h 3g 4d 4e 4g 4h 4m 3l 1k 2k 1l 2l 2m 1n 2n 1p 2p 3t 2r 4n 3r sa v ss sa sa sa sa dqc dqc dqc dqc dqc dqc dqc dqc dqc sbw c tnc(*) ss c c sw sbw d dqd dqd dqd dqd dqd dqd dqd dqd dqd sa sa sa m1 sa v ss sa sa sa sa dqb dqb dqb dqb dqb dqb dqb dqb dqb sbw b g k k sbw a dqa dqa dqa dqa dqa dqa dqa dqa dqa zz sa sa sa sa m2 5b - 5a 5c 6c 6a 6d 7d 6e 7e 6f 6g 7g 6h 7h 5g 4f 4k 4l 5l 7k 6k 7l 6l 6m 7n 6n 7p 6p 7t 5t 6r 4t 4p 5r 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
128kx36, sync lw, lvttl, rev 4.6 21 / 22 august 12, 1998 sony ? CXK77B3641GB ordering information. note (*): contact sony memory marketing for availability of -5 speed bin. part number speed register - register register - latch/ register - flow thru CXK77B3641GB-45 4.5ns cycle / 2.4ns access 5.5ns cycle / 5.5ns access CXK77B3641GB-5 (*) 5.0ns cycle / 2.5ns access 5.7ns cycle / 5.7ns access CXK77B3641GB-6 6.0ns cycle / 3.0ns access 6.0ns cycle / 6.0ns access sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu s- trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circui ts.
128kx36, sync lw, lvttl, rev 4.6 22 / 22 august 12, 1998 sony ? CXK77B3641GB revision history rev. # rev. date changes / modifications to data-sheet rev 4.0 8/22/97 initial version, based on ts-2 evaluation rev 4.2 (unreleased) 11/21/97 modified ac electrical characteristics: r-l, r-ft modes: -6 t klqv , t glqv, t ghqz 3.0ns to 2.5ns t khqz , t khqz1 3.0ns to 2.0ns t khqx1 2.0ns to 3.0ns renamed -4.5 bin to -45 bin in all modes. renamed -5 bin to -50 bin in all modes. renamed -6 bin to -60 bin in all modes. added -65 bin to all modes. provided idd & isb typical values (page-7) provided pecl dc electrical characteristic (page-6) provided pecl ac test conditions (page-10, -11) rev 4.3 01/05/98 updated dc recommended operating conditions (page-6) updated ac test conditions for v ddq = 2.5v (page-10) rev 4.4 01/15/98 deleted -65 bins. rev 4.5 03/12/98 renamed -50 bin to -5 bin in all modes. renamed -60 bin to -6 bin in all modes. changed bscan register # 52 from v ss to tnc (page-20) modified bscan register table to include tnc (page-19) t khqz & t khqz1 ac timing changed to 2.0ns for all bins (page-8 &-9) changed v dif (min) dc parameter from 0.4v to 0.5v (page-6) changed v cm (min) dc parameter from 1.2v to 1.15v (page-6) changed v cm (typ) dc parameter from v ddq /2 to 1.4v (page-6) deleted lvttl clock v ih and v il dc parameters (page-6) added lvttl clock v kin dc parameter (page-6) added lvttl clock v x dc parameter (page-6) added note 5 (clock description) to dc recommendations (page-6) rearranged ac test conditions (page-10 & page-11) removed preliminary from the spec. rev 4.6 08/12/98 modified ac electrical characteristics: r-r mode: -45 t khqv 2.3ns to 2.4ns

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